Embedded Systems Interview Questions India 2026: Microcontrollers, RTOS, and Communication Protocols

The distinction between microcontrollers and microprocessors is a fundamental embedded systems interview question.

Microcontroller vs Microprocessor:

1. Microprocessor: only the CPU; requires external memory (RAM, ROM, flash), external I/O peripherals, and support chips. Examples: Intel Core i7, ARM Cortex-A53 (used in Raspberry Pi). Used for general-purpose computing where you need high performance and an operating system
2. Microcontroller: integrates CPU, RAM, ROM/flash, timers, ADC/DAC, UART, SPI, I2C, GPIO all on a single chip. Examples: STM32 (ARM Cortex-M), PIC, AVR (Arduino), ESP32. Used for embedded control applications where cost, power, and size matter
3. Key trade-off: microcontrollers are cheaper and lower power; microprocessors are more powerful

Memory types in embedded systems:

1. ROM (Read-Only Memory): stores the program code (flash in modern MCUs); non-volatile (retains data without power)
2. RAM (Random Access Memory): stores runtime data (stack, heap, global variables); volatile (loses data without power)
3. Flash: electrically erasable programmable ROM used in modern MCUs; can be erased and reprogrammed; stores firmware
4. EEPROM: electrically erasable byte-by-byte; used for storing configuration data that persists across power cycles
5. Stack: used for local variables and function call frames; grows downward in most ARM architectures
6. Heap: used for dynamic memory allocation (malloc/free); avoid in RTOS systems due to fragmentation

Memory-mapped I/O:

1. Peripheral registers (GPIO, UART, SPI, ADC) are mapped to specific memory addresses in the MCU's address space
2. You read from and write to peripheral registers by reading and writing to these addresses in C
3. The volatile keyword: always use volatile for variables that map to hardware registers to prevent the compiler from caching or optimising away reads
4. Example: volatile uint32t *gpioodr = (volatile uint32t *)0x40020014; *gpioodr |= (1 << 5); // Set pin 5 high
5. Bit manipulation: embedded programming relies heavily on bit manipulation: set bit (reg |= (1 << n)), clear bit (reg &= ~(1 << n)), toggle bit (reg ^= (1 << n)), test bit (reg & (1 << n))

RTOS concepts and interrupt handling are core embedded systems interview topics at Bosch India, Qualcomm India, and automotive electronics companies.

RTOS (Real-Time Operating System):

1. An RTOS provides deterministic scheduling — tasks run within guaranteed time bounds (deadlines)
2. Task: the basic unit of execution in an RTOS (equivalent to a thread in Linux)
3. Priority-based preemptive scheduling: the highest-priority ready task always runs; a lower-priority task is preempted when a higher-priority task becomes ready
4. FreeRTOS: the most widely used open-source RTOS in India; used on STM32, ESP32, and many other MCUs
5. xTaskCreate(): create a task in FreeRTOS; parameters: task function, name, stack size, parameters, priority, task handle
6. vTaskDelay(pdMSTOTICKS(100)): delay a task for 100 milliseconds without blocking other tasks
7. Mutex: mutual exclusion; only the task that took the mutex can give it back; used to protect shared resources
8. Semaphore: counting or binary; used for signalling between tasks (e.g., an ISR gives a semaphore; a task waits on it)
9. Message queue: a FIFO buffer for passing data between tasks; xQueueSend() and xQueueReceive()
10. Priority inversion: a high-priority task is blocked waiting for a resource held by a low-priority task; a medium-priority task preempts the low-priority task; the high-priority task is indirectly blocked. Solution: priority inheritance (the mutex holder temporarily inherits the priority of the highest waiter)

Interrupt handling:

1. ISR (Interrupt Service Routine): a function that executes in response to a hardware interrupt (GPIO edge, UART receive, timer overflow)
2. ISR rules: keep ISRs short and fast; never block in an ISR (no delay, no mutex wait, no malloc)
3. Deferred interrupt processing: use a flag or give a semaphore in the ISR; a task waits on that semaphore and does the heavy work
4. Interrupt priority: MCUs (ARM Cortex-M) have configurable interrupt priorities; higher-priority interrupts can preempt lower-priority ISRs
5. Nested interrupts: enabled when an ISR allows higher-priority interrupts to fire during its execution

Watchdog timer:

1. A hardware timer that resets the MCU if software fails to periodically reset (pet/kick) it
2. Prevents system lockup: if the firmware hangs (infinite loop, deadlock), the watchdog fires and resets the MCU
3. Independent watchdog (IWDG): clocked by an independent oscillator; cannot be disabled by software; resets the MCU if not refreshed within the timeout
4. Window watchdog (WWDG): must be refreshed within a specific time window (not too early, not too late); detects timing anomalies

Communication protocols are a mandatory topic in embedded systems interviews. Understand the trade-offs between SPI, I2C, UART, and CAN.

UART (Universal Asynchronous Receiver-Transmitter):

1. Asynchronous: no shared clock signal; both devices agree on baud rate (bits per second: common values are 9600, 115200)
2. Two wires: TX (transmit) and RX (receive); cross-connected between devices (device A TX to device B RX)
3. Full-duplex: can transmit and receive simultaneously
4. Data frame: start bit, 5-9 data bits, optional parity bit, 1-2 stop bits
5. Used for: debug consoles, GPS modules, Bluetooth HC-05 modules

SPI (Serial Peripheral Interface):

1. Synchronous: shared clock (SCLK) line; data is sampled on clock edges
2. Four wires: MOSI (Master Out Slave In), MISO (Master In Slave Out), SCLK, CS/SS (Chip Select; one per slave)
3. Full-duplex: simultaneous transmit and receive
4. No addressing: the master selects a slave by pulling its CS line low
5. Fast: typically 1-70 MHz; much faster than I2C
6. Used for: flash memory, SD cards, LCD displays, ADCs

I2C (Inter-Integrated Circuit):

1. Synchronous, two wires: SDA (data) and SCL (clock); both are open-drain with pull-up resistors
2. Multi-master, multi-slave: up to 127 devices on the same bus using 7-bit addressing
3. Half-duplex: only one direction at a time
4. Speeds: 100 kHz (standard), 400 kHz (fast), 1 MHz (fast-plus), 3.4 MHz (high-speed)
5. Clock stretching: a slave can hold SCL low to pause the master when it needs more time to process
6. Used for: sensors (temperature, pressure, IMU), EEPROMs, RTC modules, small OLEDs

CAN (Controller Area Network):

1. Differential bus (CAN-H and CAN-L); two wires; terminated with 120-ohm resistors at each end
2. Message-based: no addresses for nodes; each message has a CAN ID (11-bit standard or 29-bit extended)
3. Priority arbitration: lower CAN ID = higher priority; arbitration is lossless (the losing sender retries automatically)
4. Multi-master: any node can transmit when the bus is idle
5. Error detection: CRC, bit stuffing, acknowledgement; high reliability
6. Speeds: up to 1 Mbps (classical CAN); CAN FD supports up to 5-8 Mbps in the data phase
7. Used for: automotive ECUs (Engine Control Unit), industrial automation, robotics; mandatory knowledge at Bosch India